applications ? test equipment ? data acquisition ? scientific instruments ? medical instruments ? seismological equipment ? robotic systems ? weighing systems features ? 24 bit resolution ? software selectable features ? 0.5ppm/c max. scale factor error ? 2 ppm max. linearity error ? auto zero ? bus compatible ? internal clock and reference ? low power consumption (0.450 watts) ADC150c -25c to +85c 60ppm ADC150ca -25c to +85c 30ppm ADC150m -55c to +125c 100ppm temperature max. scale type operating range factor deviation description ADC150 is a high performance programmable 24- bit integrating a/d converter based on a patented architecture. the integration time and resolution along with the power line cycle selection can be easily programmed through the mode control byte. ADC150 offers 2 ppm max. linearity error and 1 ppm/c max. scale factor error over the military temper ature range. it also has excellent offset stability at 2 ppm max. which the user can auto zero if desired. ADC150's compatibility with popular microcomputer bus es increases its ease of application in smart systems. an on-board microprocessor controls all internal functions of the ADC150. thaler designers have minimized external connections to greatly reduce the problem often encountered when applying adc's. operating from 15vdc and a +5vdc power supply, ADC150 is packaged in a hermetically sealed 40-pin ceramic dip package. precision test equipment, sci entific and medical instruments, and data acquisition systems are primary application areas for the unusually high resolution and accuracy of this adc. thaler corporation. represented by: rhopoint components ltd. www.rhopointcomponents.com ADC150 programmable integrating a/d converter ADC150ds rev. f mar 00
maximum rating specifications ADC150 model ADC150 parameter temperature power supply inputs min max operating storage 125 160 units c c analog inputs digital inputs vdc vdc vdc +16 -16 +6 (top view) ADC150 notes: 1. power supply decoupling the ADC150 has internal 0.1f decoupling capacitors for all power supply inputs. the internal decoupling capacitors are adequate for applications with relatively short power supply leads (approx. 5") or if additional capacitors are located on a circuit board. for applications with long power supply leads an external capacitor of 10 f on the +/- 15v inputs and 33 f on the +5v input is recommended. 2. ground the ground connection (pin 7) should be made as solid as possible since ground noise can result in a loss of accuracy. use of a ground plane is a good approach to maintain the full accuracy of the ADC150. 3. external components a .68 f polystyrene integration capacitor must be connected to pins 34 and 35 with a lead length not exceeding 2". 4. analog inputs in order to avoid differential noise pickup it is recommended to use parallel adjacent lines for the analog inputs (pins 39, 40) on pc boards and shielded lines outside of the pc connections. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. mode control n.c. n.c. n.c. n.c. alternate input d0 d1 d2 d5 d4 d3 d6 d7 gnd analog low analog high auto zero reset status 1 status 0 convert output enable vee (-15v) vee (+15v) vdd (+5v) integration capacitor external connections n.c. n.c. v cc v ee v dd v ee 0 v cc v dd n.c. n.c. +14 -14 +4 -55 0 ADC150ds rev. f mar 00
electrical specifications model parameter accuracy temperature stability time stability error all sources conversion time warm-up time temperature range convert input auto zero input digital outputs digital inputs power supply currents power supply voltages analog input characteristics power supply rejection resolution input equivalent noise offset without auto zero offset with auto zero full scale noise (.1-10hz) @ 10v nonlinearity normal mode rejection offset full scale offset full scale min max typ min max typ min max typ ADC150c ADC150ca ADC150m bits v ppm ppm ppm vpp ppm db 1 6 1 * * * * * * * * * * 60 * * 0.2 0.1 * 1.0 0.5 * ppm/ o c ppm/ o c .1 2 ppm/24 hrs. ppm/month .0005, 2 .0003, 2 %, +/- counts 24 hrs, +/- 1 deg. c amb. 90 days, +/- 5 deg. c amb. 1 year, +/- 5 deg. c amb. .0010, 2 .0008, 2 * .0015, 2 .0013, 2 %, +/- counts %, +/- counts * * 1067 ms * 5 * ** minutes +/- 15 vdc 5 vdc 80 80 ** db ** db low high low high low high low high -25 85 * * -55 125 v v v v v v v v 0.8 * 4.0 * 0.8 * * 4.0 ** 4.0 ** 4.0 * * * * 0.8 ** 0.8 ** +15 v 23 **ma -15 v 24 ** ma 5 v 42 ** ma +15 v -15 v 5 v 14.5 15 15.5 * * * * * * v 14.5 15 15.5 *** *** v 4.5 5 5.5 *** *** v input range -10.485760 10.485755 3 **** v bias current 1.2 ** na input impedance 200 ** g ? 2 0.5 50 * * same as ADC150c note: 1) 60 cycle 2) ( max-min value) - noise(.1-10hz) ADC150 (vps = +/- 15v, + 5v, t = 25 deg. c.) * * * * 4 1 100 2 1 o c 2 24 * * 18 ADC150ds rev. f mar 00
theory of operation the timing control circuitry governs the counters that measure the integration time in both directions. the ADC150's on-board microprocessor is used to calculate the results of the integration equation and perform error corrections. note that the p automatically performs an auto zero function at start- up, but it is recommended to achieve maximum accuracy, that an auto zero be performed again after the ADC150 is fully warmed up. when the p detects a convert signal, it lowers the status lines to indicate that the adc is involved in a conversion. when it detects a change in slope direction, the p will collect the counts for the integration time. when sufficient counts have been collected, the p performs the calculations described above. when the calculations are complete, the p places the most significant byte in the output buffer and raises the s 0 flag. when another pulse is placed on the convert line, the middle byte is placed on the output, the s 0 flag is lowered and the s 1 flag raised. when the last pulse is placed in the convert line, the least significant byte is placed in the output buffer and both status flags are high indicating that the ADC150 is ready for another conversion. status line summary: figure 1. block diagram conversion in progress. conversion complete. msb in output. middle byte in output register. lsb in output. ready for next conversion. 0 0 0 1 1 0 1 1 s 1 s 0 t p = in the ADC150 block diagram (see figure 1), v hi and v low are the inputs. both are buffered and fed into a differential, voltage controlled, single output current source. this current is added to the reference current at the input of the op amp integrator. the output of the integrator is fed into a schmitt trigger, which in turn, is fed into the adc's timing control circuitry. when the integrator output actuates the schmitt trigger, the timing circuit changes the direction of the reference current source and the integrator begins integrating in the opposite direction. this continues until the schmitt trigger is actuated again by the integrator and reverses the direction of the reference current. the equation for integration times are: v x c i ref + i inp t m = v x c -i ref + i inp resolving these equations produces: i inp = i ref t p -t m t p + t m auto zero switch schmitt trigger bidirectional reference current source current directional switch timing control and counter microprocessor output buffer clock differential voltage controlled current source v hi v low +15v -15v auto zero convert status lines output enable data output ? ? ? v = voltage c= integration capacitor value i ref = reference current i inp = input current t p = time positive t m = time negative ADC150ds rev. f mar 00
connecting the ADC150 power supplies the power supply lines are connected to pins 4-7. pin 4 is -15v, pin 5 is +15v, pin 6 is +5v and pin 7 is gnd. output data lines the output data is available in byte form on pins 13-20. pin 20 is the most significant bit and pin 13 the least significant bit. the data lines go to a high impedance state when the output enable line is at a logic one level. output enable (pin 21) data is placed on the output data lines by a logic zero on this line. see figure 2 for data output format. convert (pin22) this line is used to initiate a conversion cycle and to retrieve the output data. the status lines indicate which function will be exec uted. the first pulse (transition from logic one to logic zero) starts the conversion cycle. two subsequent pulses are used to place the lower two bytes on the output data lines. see figure 4 for timing diagram. status lines (pins 23, 24) these lines indicate the present state of the adc. when the convert line receives the first pulse in a conversion cycle the status lines go to logic zero, indicating that a conversion cycle is in progress. when the conversion is complete the microprocessor places the msb of the output data in the output buffer and then raises s 0 to a logic one, indicating that the msb at the output data is available in the output buffer. when the convert line is pulsed again the middle byte of the output data is placed in that output buffer and s 1 changes to logic one and s 0 to logic zero. the third pulse places the lsb of the output data in the buffer and both status lines go to the logic one. the converter is now ready for the next conversion cycle. see figure 5 for timing diagrams. the table below shows a summary of the status code. conversion in process. conversion complete. msb in output. middle byte in output register. lsb in output. ready for next conversion. 0 0 0 1 1 0 1 1 s 1 s 0 mode control (pin 25) this line is used to program the ADC150. the mode control byte (8 bit) is placed on the data bus. pin 25 is then set to logic high, pin 21 is pulsed low to accept the control byte. pin 22 is then pulsed low and held low until the status lines return high (~2ms). pin 21 is then pulsed high and pin 25 is then returned to logic low. the ADC150 has now been reset to the new parameters. see figure 6 for timing diagrams. the mode control byte is defined as follows: bits 7 and 6 - unused bits 5 and 4 - 00 pin 39 signal input, autozero* 01 pin 38 signal input bit 3 - 0 60 hz.* 1 50 hz. bits 2,1, 0 - 001 18 bit 010 20 bit 011 22 bit* 100 24 bit * factory default settings auto-zero / reset (pin 29) a logic zero on this input will autozero the ADC150 by internally connecting the analog high to analog low. since the p is reset, the ADC150 reverts to the factory default settings in the eprom (ie. 22bits, 60hz, pin 39 analog high). to select a mode different than the default settings, the mode control must be set after auto zero. see figure 3 for timing diagrams. integration capacitor (pin 34, 35) a 0.68 f polystyrene or mylar must be connected to these pins. lead length should be as short as possible and not exceed 2". analog inputs (pin 39, 40) both analog inputs are buffered by op-amps and have a common mode rejection of approximately 80db minimum. to maintain the full accuracy at the adc it is recommended to keep the input to analog low to less than 0.1vdc. ADC150ds rev. f mar 00
output data representation the output data is represented in bob (bipolar offset binary) format. the table below shows the output data codes for zero and plus-minus full scale input voltage for the programmable resolution of the converter. input voltage output data high byte middle byte low byte 00 80 ff 00 00 ff 00 00 ff -10.485760 v 0.0 v +10.485755 v input voltage output data high byte middle byte low byte 00 20 3f 00 00 ff 00 00 ff -10.485760 v 0.0 v +10.485755 v input voltage output data high byte middle byte low byte 00 08 10 00 00 ff 00 00 ff -10.485760 v 0.0 v +10.485755 v input voltage output data high byte middle byte low byte 00 02 04 00 00 ff 00 00 ff -10.485760 v 0.0 v +10.485755 v 24 bits 1 lsb = 1.24 v 22 bits 1 lsb = 5 v 20 bits 1 lsb = 20 v 18 bits 1 lsb = 80 v figure 2 ADC150ds rev. f mar 00
timing diagrams figure 3. auto zero convert s1 s0 az t trst t azd t az symbol parameter min. typ. max. unit t azd az pulse width 0.2 s t trst tristate time 30 ms t az az time 400 ms figure 4. conversion (22 bits) s1 s0 convert t conz t sz t conv symbol parameter min. typ. max. unit t conz convert pulse 5.0 s t sz status delay 8.0 s t conv convert time 320 ms ADC150ds rev. f mar 00
timing diagrams figure 5. data output convert s1 s0 oe d0 - d7 mib t oedv t sir t sir msb lsb symbol parameter min. typ. max. unit t oedv oe delay 45 ns t sir status delay 3.0 s cnvrt s1 s0 mode figure 6. mode change oe symbol parameter min. typ. max. unit t sir status delay 8.0 s t sl status low 100 ms t oedv oe delay 45 ns t sl t oedv t sir ADC150ds rev. f mar 00
resolution 18 bits 20 bits 22 bits 24 bits line cycles 1 4 16 64 conv. / sec (60/50 hz) 60 / 50 15 / 12 3.7 / 3.1 1.2 / .93 line cycle at 60 hz = 16.667 ms; 50 hz = 20 ms figure 7. integration times figure 8. mechanical specifications dim inches min max e d a l b q c p g1 1.080 1.100 2.075 2.115 0.155 .100 typ .018 typ .015 .009 .012 .890 0.185 .035 .012 .018 .910 40-pin hybrid package b1 .040 typ b2 0.220 0.240 notes: 1. gold plating 60 micro inches minimum thickness over 100 micro inches nominal thickness of nickel ADC150ds rev. f mar 00
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